EP1C12Q240I6 vs EP1C12Q240I8ES 比較
詳細並排比較 EP1C12Q240I6 由 Altera 與 EP1C12Q240I8ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1C12Q240I6 | EP1C12Q240I8ES |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Cyclone FPGA | — |
| Logic Elements | 12,060 | — |
| Total RAM Bits | 239,616 bits | — |
| Embedded M4K RAM Blocks | 52 | — |
| Maximum User I/O | 249 | — |
| PLLs | 2 (with 4 outputs each) | — |
| Maximum Internal Frequency | 405 MHz | — |
| Process Technology | 130 nm | — |
| Core Voltage | 1.5 V | — |
| Package Type | 240-pin PQFP (Plastic Quad Flat Pack) | — |
| Terminal Form | Gull Wing | GULL WING |
| Temperature Grade | Industrial (I) | — |
| Speed Grade | 6 | 8 |
| I/O Standards Supported | LVDS, PCI, SSTL-2, LVTTL, LVCMOS | — |
| Configuration Methods | AS, PS, JTAG (IEEE 1149.1) | — |
| Embedded Multipliers | [DATA_NEEDED: 18x18 multiplier count] | — |
| RoHS 狀態 | [DATA_NEEDED] | unknown |
| Manufacturer | — | Intel |
| Manufacturer Part Number | — | EP1C12Q240I8ES |
| FPGA Family | — | Cyclone |
| Programmable Logic Type | — | FPGA (field-programmable gate array) |
| Configuration Type | — | SRAM-based |
| FPGA Process | — | 1.5-V, 0.13-um, all-layer copper SRAM process |
| Maximum Family Logic Elements | — | 20,060 LEs |
| Maximum Family Embedded RAM | — | 288 Kbits |
| EP1C12 Delivered Logic Elements | — | [DATA_NEEDED: EP1C12 exact LE count] |
| Package Code | — | FQFP |
| Package Description | — | 240-pin square QFP (PQFP/FQFP) |
| Number of Terminals | — | 240 |
| Package Shape | — | Square |
| JESD-609 Code | — | e0 |
| Maximum Supply Voltage | — | 1.575 V |
| Nominal Core Supply Voltage | — | 1.5 V |
| Temperature Grade Code | — | I (industrial) |
| Ordering Code Variant | — | ES (engineering sample) |
| Minimum Operating Temperature | — | [DATA_NEEDED: minimum operating temperature] |
| Maximum Operating Temperature | — | [DATA_NEEDED: maximum operating temperature] |
| Supported Configuration | — | Configuration and JTAG boundary-scan testing supported |