EP1K100QI208-2 vs EP1K100QI208-2N 比較

詳細並排比較 EP1K100QI208-2 由 Altera 與 EP1K100QI208-2N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1K100QI208-2 EP1K100QI208-2N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Obsolete
Family ACEX-1K —
Logic Elements 4,992 cells —
System Gates 100,000 257000
Logic Array Blocks (LABs) 624 —
Embedded Memory (EAB) 49,152 bits —
User I/Os 147 —
Maximum Operating Frequency 250 MHz —
Core Voltage (VCCINT) 2.5 V —
Process Technology 0.22 umm CMOS SRAM —
封裝 208-pin PQFP (BFQFP) —
Pitch 0.5 mm —
安裝類型 Surface Mount Surface Mount
工作溫度 -40C to +85C (Industrial) —
Configuration Interface JTAG (IEEE 1149.1) / serial / EPC2 —
Global Clock Networks 4 —
I/O Standards Supported LVTTL, LVCMOS, PCI, 5V tolerant —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: manufacturer RoHS certificate]
Series — ACEX-1K
FPGA Family — ACEX-1K
Number of Logic Elements/Cells — 4992
Number of LABs/CLBs — 624
Total RAM Bits — 49152
Number of User I/O — 147
封裝 / 外殼 — 208-BFQFP
Core Supply Voltage — 2.5 V
Speed Grade — -2
Temperature Grade — I (industrial)
Typical Gate Count — 100K gates (family)
工作溫度範圍 — [DATA_NEEDED: exact industrial temperature limits from ACEX-1K datasheet]
Max User I/O in 208-BFQFP — 147
Total Number of Configuration Bits — [DATA_NEEDED: configuration bitstream size]
Maximum Internal Clock Frequency — [DATA_NEEDED: clock frequency for -2 speed grade]
I/O Standard Support — [DATA_NEEDED: supported I/O standards]
PLL/Clock Management — [DATA_NEEDED: PLL availability on EP1K100]

資料表與資源

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