EP1K50QC208-2N vs EP1K50QI208-2 比較

詳細並排比較 EP1K50QC208-2N 由 Intel 與 EP1K50QI208-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1K50QC208-2N EP1K50QI208-2
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Series ACEX-1K ACEX 1K
Family ACEX 1K —
Logic Elements 2,880 —
Typical Gates 50,000 —
Logic Array Blocks (LABs) 360 360
Embedded Memory (EAB SRAM) 40 kbit —
User I/Os 147 —
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Maximum Toggle Frequency 200 MHz —
Pin-to-Pin Delay (LE) 0.4 ns (per data sheet snippet) —
Process Technology 0.22 µm CMOS CMOS, SRAM-based configuration
Core Supply Voltage 2.5 V —
I/O Supply Voltage [DATA_NEEDED: I/O supply voltage] —
Configuration Interface JTAG (IEEE 1149.1), Serial (PS/AS) —
封裝 208-pin PQFP (BFQFP) —
安裝類型 Surface Mount (Gull-Wing) Surface Mount
工作溫度 0 °C to 85 °C (Commercial) -40C to +85C (industrial)
MSL 等級 [DATA_NEEDED: MSL level] —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Manufacturer — Altera (Intel)
Typical Gate Count — 50,000 gates
Logic Elements (LEs) — 2,880
Embedded SRAM — 40,960 bits
Maximum User I/O Pins — 147
Speed Grade — -2
Core Voltage — 2.5 V
I/O Voltage Support — 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Package Type — 208-pin PQFP (Power Quad Flat Pack)
Configuration Method — JTAG / serial configuration PROM (EPC2/EPCS)

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