EP1M120B484C5 vs EP1M120B484C6 比較
詳細並排比較 EP1M120B484C5 由 Intel 與 EP1M120B484C6 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1M120B484C5 | EP1M120B484C6 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Mercury (EP1M) | Mercury (ACEX 1M) |
| Logic Elements | 4,800 | — |
| Typical Gates | 120,000 | — |
| Maximum User I/O | 303 | — |
| 封裝 | FineLine BGA-484 (19 mm x 19 mm, 1.0 mm pitch) | 484-ball FineLine BGA (BGA-484) |
| 工作溫度 | 0C to +85C (commercial) | — |
| Speed Grade | 5 (slowest) | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.18 um CMOS | — |
| PLLs | 4 | — |
| Embedded RAM Bits | 49,152 | — |
| True LVDS Channels | Up to 34 pairs | — |
| Maximum LVDS Data Rate | 840 Mbps per channel | — |
| Configuration Scheme | Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG | — |
| Peak Reflow Temperature | 220 C | 220 °C |
| Lead-Free / RoHS | SnPb ball finish (non-RoHS by default) | — |
| Multipliers | Embedded in system blocks for DSP | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Logic Elements (typical) | — | 120 LE |
| Maximum Logic Elements | — | [DATA_NEEDED: maximum logic elements] |
| Flip-Flops | — | 4,800 |
| User I/O Pins (max) | — | 303 |
| Configuration Memory | — | SRAM-based (volatile, re-load on power-up) |
| Operating Temperature Grade | — | Commercial (C suffix) |
| Process Node | — | 0.18 µm |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Configuration Modes | — | PS, AS, JTAG |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |
| Design Software | — | Quartus II (legacy support required) |