EP1M120F484C7 vs EP1M120B484C6 比較
詳細並排比較 EP1M120F484C7 由 Altera 與 EP1M120B484C6 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1M120F484C7 | EP1M120B484C6 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Mercury (EP1M) | Mercury (ACEX 1M) |
| Logic Family | CMOS | — |
| Logic Elements | 49,152 | — |
| Number of LABs | 480 | — |
| User I/Os | 303 | — |
| 腳位數 | 484 | — |
| Package Type | FineLine BGA (FBGA-484) | — |
| Core Supply Voltage | 1.8 V | — |
| 工作溫度 | 0 C to 85 C (Commercial) | — |
| High-Speed Transceivers | Integrated, CDR up to 1.25 Gbps | — |
| Configuration | JTAG / Active Serial (per datasheet) | — |
| Device Type | Loadable PLD (FPGA) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Country of Origin | [DATA_NEEDED: COO] | — |
| Logic Elements (typical) | — | 120 LE |
| Maximum Logic Elements | — | [DATA_NEEDED: maximum logic elements] |
| Flip-Flops | — | 4,800 |
| User I/O Pins (max) | — | 303 |
| Configuration Memory | — | SRAM-based (volatile, re-load on power-up) |
| 封裝 | — | 484-ball FineLine BGA (BGA-484) |
| 安裝類型 | — | Surface Mount |
| Peak Reflow Temperature | — | 220 °C |
| Operating Temperature Grade | — | Commercial (C suffix) |
| Process Node | — | 0.18 µm |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Configuration Modes | — | PS, AS, JTAG |
| Design Software | — | Quartus II (legacy support required) |