EP1S10F484C5N vs EP1S10F484C6N 比較
詳細並排比較 EP1S10F484C5N 由 Intel 與 EP1S10F484C6N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1S10F484C5N | EP1S10F484C6N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | Stratix | — |
| Family | Stratix (original) | Stratix |
| Logic Elements (LEs) | 10,570 | — |
| Logic Array Blocks (LABs) | 1,057 | — |
| Embedded Memory Bits | 920,448 | — |
| TriMatrix Memory Blocks | 14 | — |
| Embedded DSP Blocks | 6 (≈48 9-bit multipliers) | — |
| PLLs | 4 | — |
| Global Clock Networks | 12 | — |
| Maximum User I/O | 335 | — |
| User I/O Standard Support | LVDS, LVPECL, PCI-X, RapidIO, DDR | — |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Core Voltage (VCCINT) | 1.5 V | — |
| Maximum Internal Frequency | 500 MHz (per Stratix datasheet) | — |
| Operating Temperature (TJ) | 0 °C to 85 °C (Commercial) | — |
| 封裝 | 484-ball FCBGA (F484), 23 x 23 mm, 1.0 mm pitch | 484-FBGA (23 × 23 mm, 1.0 mm pitch) |
| 安裝類型 | Surface Mount | Surface Mount (SMT) |
| Configuration Method | JTAG / Passive Serial / Active Serial | SRAM - volatile (JTAG / passive serial / passive parallel / fast passive parallel) |
| Device Status | Obsolete - last time buy completed | — |
| Design Toolchain | Quartus II (≤ v13.0) | — |
| Logic Elements / Cells | — | 10,570 |
| Number of LABs / CLBs | — | 1,057 |
| Total RAM Bits | — | 920,448 |
| Number of User I/O | — | 335 |
| Supply Voltage - Operating | — | 1.425 V to 1.575 V (core 1.5 V) |
| Speed Grade | — | C6 |
| 工作溫度 | — | 0 °C to 85 °C (TJ) |
| Lead Free | — | Yes |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS |
| On-chip Resources | — | TriMatrix memory (M512, M4K, M-RAM), DSP blocks, PLLs |