EP1S10F672I7 vs EP1S10B672C7N 比較
詳細並排比較 EP1S10F672I7 由 Intel 與 EP1S10B672C7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1S10F672I7 | EP1S10B672C7N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | NRND |
| Family | Stratix | — |
| Logic Elements | 10,570 | — |
| User I/O Pins | 345 | — |
| 封裝 | FBGA-672, 35 x 35 mm, 1.27 mm pitch | — |
| 工作溫度 | 0 C to +85 C (industrial grade, I7) | — |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Process Technology | 0.13 um CMOS | — |
| Maximum Internal Clock | 420.17 MHz (per datasheet) | 420.17 MHz |
| Logic Family | CMOS | CMOS |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Total Pins | 672 (FBGA) | — |
| Configuration Method | JTAG / serial / parallel PROM | — |
| 記憶體類型 | TriMatrix embedded block RAM + distributed RAM | — |
| DSP Blocks | Yes (dedicated hardware multipliers) | — |
| 安裝類型 | Surface Mount (BGA) | — |
| RoHS 狀態 | unknown - verify per lot | — |
| Manufacturer | — | Intel / Altera |
| Product Family | — | Stratix |
| Logic Elements/Cells | — | 10570 cells |
| Technology Node | — | 130 nm |
| Package Code | — | BGA |
| Number of Terminals | — | 672 |
| Package Body Size | — | 35 x 35 mm |
| Ball Pitch | — | 1.27 mm |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial extended, 0 to 85 C |
| Terminal Form | — | Ball |
| Configuration/JTAG | — | JTAG boundary-scan per Stratix family data sheet |
| Number of User I/O in 672-BGA | — | [DATA_NEEDED: user I/O count] |
| Total RAM Bits | — | [DATA_NEEDED: total RAM bits] |
| Embedded PLLs | — | [DATA_NEEDED: PLL count] |
| Config Device Compatibility | — | [DATA_NEEDED: supported configuration devices] |
| RoHS | — | unknown - N suffix may indicate Pb-free, not verified in fetched data |