EP1S20F672C6 vs EP1S20F672C7N 比較
詳細並排比較 EP1S20F672C6 由 Altera 與 EP1S20F672C7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1S20F672C6 | EP1S20F672C7N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Manufacturer | Altera (now Intel) | — |
| Series | Stratix | Stratix (first generation) |
| Family | Stratix (first generation) | Stratix |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Logic Array Blocks (LABs) | 1,846 | — |
| Embedded Memory Bits | 1,669,248 | — |
| Maximum User I/Os | 426 | — |
| 封裝 | 672-ball FineLine BGA | 672-FBGA (FineLine BGA) |
| Package Code | F672 | — |
| Speed Grade | C6 | C7 (-7) |
| 工作溫度 | 0°C to +85°C (Commercial) | 0°C to +85°C (commercial) |
| 供應電壓 | Core 1.5 V, I/O programmable | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | — |
| Logic Cells | — | 18,460 |
| Configurable Logic Blocks (CLBs) | — | 2,132 |
| Embedded Memory (TriMatrix) | — | 1,669,248 bits (426 Kbit total) |
| DSP Blocks | — | 56 (dedicated 18x18 multipliers) |
| Maximum User I/O | — | 586 |
| I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| PLLs | — | Up to 12 |
| Maximum Operating Frequency | — | 420.17 MHz |
| Core Voltage | — | 1.5 V |
| Package Body Size | — | 35 mm x 35 mm |
| Ball Pitch | — | 1.27 mm |
| Lead-Free / RoHS | — | Yes (lead-free finish, RoHS compliant) |
| Configuration Modes | — | PS, PPS, FPP, JTAG |
| MSL 等級 | — | [DATA_NEEDED: moisture sensitivity level] |