EP1S40F1020C6 vs EP1S40F1020C5GA 比較

詳細並排比較 EP1S40F1020C6 由 Altera 與 EP1S40F1020C5GA 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1S40F1020C6 EP1S40F1020C5GA
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family Stratix (original, EP1S) —
Logic Elements (LE) 41,250 41,250
Logic Array Blocks (LABs) 4,125 —
Embedded Memory Bits 3,423,744 bits (TriMatrix: M512 + M4K + M-RAM) —
Maximum User I/O 773 —
封裝 1020-BBGA, FC-FBGA, 33 x 33 mm, 1.0 mm pitch 1020-BBGA (FineLine BGA)
Process Technology 0.13 µm CMOS —
Core Voltage 1.5 V —
工作溫度 0 °C to +85 °C (commercial) 0C to +85C (Commercial)
Maximum Frequency 450.05 MHz —
Supply Voltage (Core) 1.5 V [DATA_NEEDED: VCCINT value]
I/O Standards LVTTL, LVCMOS, LVDS, SSTL, HSTL, PCI, PCI-X —
安裝類型 Surface Mount (FCBGA) Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating from datasheet] [DATA_NEEDED: MSL rating]
RoHS 狀態 [DATA_NEEDED: RoHS status from official datasheet] Unknown - non-GA suffix commercial part
Series — Stratix
Total RAM Bits — 3,423,744
User I/O Count — 773
Speed Grade — C5
Process Node — 0.13 µm CMOS with 9-layer metal
I/O Bank Count — [DATA_NEEDED: bank count]
DSP Blocks — Embedded multiplier blocks (count per Stratix datasheet family)
PLL Count — Up to 12 enhanced PLLs (per Stratix family)
High-Speed Transceivers — Up to 12 channels (per Stratix family, variant dependent)
Configuration Method — JTAG, Passive Serial, Altera EPC device
Lead-Free — Yes (per Altera/Intel policy at release)

資料表與資源

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