EP1SGX40DF1020C5N vs EP1SGX40DF1020C5ES 比較

詳細並排比較 EP1SGX40DF1020C5N 由 Intel 與 EP1SGX40DF1020C5ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。

Intel

EP1SGX40DF1020C5N - Stratix GX FPGA 41,250 LEs | Altera / Intel

EP1SGX40DF1020C5N Obsolete

Intel

EP1SGX40DF1020C5ES ✓ 啟用中

參數	EP1SGX40DF1020C5N	EP1SGX40DF1020C5ES
品牌	Intel	Intel
類別	FPGA & CPLD	FPGA & CPLD
生命週期狀態	Obsolete	啟用中
Series	Stratix GX	—
Logic Elements	41,250	—
Number of LABs/CLBs	4,125	—
Total Memory Bits	3,423,744	—
Number of I/O	624	—
封裝	1020-BBGA (FC-FBGA), 33 x 33 mm, 1 mm pitch	—
安裝類型	Surface Mount	—
Process Technology	130 nm CMOS	130 nm
Core Supply Voltage	1.5 V	—
工作溫度	0C to 85C (Commercial)	0 C to 85 C
Speed Grade	C5	—
Logic Family	CMOS	Stratix GX
Programmable Type	In-System Programmable	—
Transceivers	Embedded multi-gigabit serial transceivers	—
Configuration	JTAG / EPCS serial	—
RoHS 狀態	Compliant (lead-free)	unknown
Product Type	—	Field-Programmable Gate Array (FPGA)
Logic Technology	—	CMOS
Logic Cells	—	41,250 cells
Logic Array Blocks	—	4,125 LABs
Configurable I/O Connections	—	624 input and 624 output connections
供應電壓	—	1.5 V
Reported Maximum Frequency	—	5,000 MHz
Reported Maximum CLB Combinatorial Delay	—	7.49 ns
Alternative Listed Maximum Clock Frequency	—	6 MHz
Terminal Count	—	1,020 pins
Package Type	—	FC-FBGA-1020
Package Dimensions	—	33 mm x 33 mm
Ball Pitch	—	1 mm
Mounting Configuration	—	Surface-mount ball grid array
Terminal Form	—	Ball
Package Code	—	BGA
Configuration Method	—	[DATA_NEEDED: configuration method]
REACH Status	—	unknown
AEC-Q100 Qualification	—	unknown