EP1SGX40DF1020I7 vs EP1SGX40G 比較
詳細並排比較 EP1SGX40DF1020I7 由 Altera 與 EP1SGX40G 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP1SGX40DF1020I7 - 41,250 LEs Stratix GX FPGA, 1.5V FC-FBGA-1020 | Altera
EP1SGX40DF1020I7 Obsolete規格比較
| 參數 | EP1SGX40DF1020I7 | EP1SGX40G |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 41,250 | 41,250 |
| Configurable Logic Blocks (CLBs) | 4,125 | — |
| Process Technology | 130 nm CMOS | [DATA_NEEDED: process node] |
| Nominal Core Supply Voltage | 1.5 V | — |
| Supply Voltage Range | 1.425 V to 1.575 V | — |
| 封裝 | 1020-ball FC-FBGA | 1020-pin FineLine BGA |
| Terminal Form | Ball | — |
| Package Shape | Square | — |
| Grading of Temperature | Military (I7 grade) | — |
| Technology | CMOS | — |
| 工作溫度 | -40 °C to +100 °C (I7 grade per family datasheet) | — |
| Combinatorial CLB Delay | 9.48 ns (per family datasheet) | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Total RAM Bits | — | 3,423,744 |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Maximum User I/O Pins | — | 624 |
| Number of Transceivers | — | 20 |
| Maximum Transceiver Data Rate | — | 3.1875 Gbps |
| Minimum Transceiver Data Rate | — | 500 Mbps |
| Transceiver Channels per Bank | — | 4 |
| Supported Serial Standards | — | PCI Express, XAUI, Serial RapidIO, SerialLite II |
| 8B/10B Encoder/Decoder | — | Hardware (dedicated per channel) |
| PLLs | — | [DATA_NEEDED: PLL count] |
| Speed Grades Available | — | C5, C6, C7, I5, I6, I7 |
| Operating Temperature Range (Commercial) | — | 0C to +85C |
| Operating Temperature Range (Industrial) | — | -40C to +100C |
| Configuration Method | — | EPC enhanced configuration devices, JTAG |
| Vertical Migration | — | Supported within 1020-pin FineLine BGA package (EP1SGX25/EP1SGX40) |