EP20K1000CF33I8N vs EP20K1000CF33C9ES 比較

詳細並排比較 EP20K1000CF33I8N 由 Altera 與 EP20K1000CF33C9ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP20K1000CF33C9ES EP20K1000CF33C9ES - APEX-20KC FPGA 1M Gates 38400 LE 1020-FBGA

EP20K1000CF33C9ES - APEX-20KC FPGA 1M Gates 38400 LE 1020-FBGA

EP20K1000CF33C9ES ⚠ 最後購買機會

規格比較

參數 EP20K1000CF33I8N EP20K1000CF33C9ES
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 最後購買
Family APEX 20KC APEX-20KC
Logic Elements 38,400 cells 38,400
System Gates 1,000,000 (approx.) —
Maximum Internal Clock Frequency 301.21 MHz —
Propagation Delay 1.79 ns —
Number of Logic Elements / Cells 38,400 —
Process Technology 0.15 µm CMOS 0.18 um CMOS
Core Supply Voltage 1.8 V nominal (1.71 V to 1.89 V) —
Number of I/O Pins 700 user I/O —
腳位數 1020 —
Package Type FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) —
工作溫度 -40 °C to +85 °C (industrial) 0 C to +85 C (commercial)
Embedded Memory Dual-port RAM via ESB blocks —
PLL Count 4 —
Configuration Interface IEEE 1149.1 JTAG, EPC serial/parallel —
安裝類型 Surface Mount —
RoHS 狀態 [DATA_NEEDED: rohs status] [DATA_NEEDED: RoHS compliance status]
Speed Grade I8 C9
Manufacturer — Intel (formerly Altera)
Typical Gate Count — 1,000,000 system gates
Logic Array Blocks (LABs) — 3,840
Embedded System Blocks (ESBs) — 212
Total Embedded RAM Bits — 327,680 bits
Maximum User I/O Pins — 708
封裝 — 1,020-ball FineLine BGA (FBGA)
Logic Element Architecture — 4-input LUT with dedicated carry chain
Maximum Embedded RAM per ESB — 32,768 bits (dual-port, FIFO support)
Phase-Locked Loops — Up to 4 enhanced PLLs
MultiVolt I/O Support — 1.8V / 2.5V / 3.3V / 5.0V
JTAG Support — IEEE 1149.1 boundary-scan
Configuration Method — Passive serial / Passive parallel / JTAG
Lead-Free — [DATA_NEEDED: lead-free finish status]

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