EP20K100QC240-1 vs EP20K100QC240-1XV 比較

詳細並排比較 EP20K100QC240-1 由 Intel 與 EP20K100QC240-1XV 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K100QC240-1 EP20K100QC240-1XV
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX 20K —
Device Type FPGA (Field-Programmable Gate Array) —
Logic Elements (LEs) 4,160 —
Typical Gates 100,000 —
Maximum User I/O 189 —
Embedded RAM Bits 53,248 —
Process Technology 0.22 µm CMOS 0.22 um CMOS
Core Supply Voltage 2.5 V —
Maximum Internal Frequency 250 MHz 250 MHz
Speed Grade -1 —
封裝 240-pin PQFP (QFP-240) 240-pin PQFP (32 x 32 mm, 0.5 mm pitch)
Package Code S-PQFP-G240 —
Terminal Form Gull Wing —
Propagation Delay 1.6 ns (per datasheet, typical) —
工作溫度 0 °C to +85 °C (Commercial) 0C to +85C (commercial) / -40C to +85C (industrial variant)
安裝類型 Surface Mount Surface Mount (gull-wing leads)
JTAG Support IEEE 1149.1 Boundary Scan —
Programming In-system (SRAM-based) via Quartus / MAX+PLUS II —
Series — APEX 20K
Device Family — APEX 20K (MultiCore architecture)
System Gates — 100,000 gates
Logic Elements (Cells) — 4,160
Embedded Memory — 53,248 bits
User I/Os — 189
Dedicated Inputs — 4
PLLs — 4
Core Supply Voltage (VCCINT) — 2.5 V nominal (2.375 V to 2.625 V)
I/O Supply Voltage (VCCIO) — 3.3 V / 5 V tolerant
Propagation Delay (tpd) — 2.5 ns
Configuration Interface — JTAG / serial (EPC configuration device)
RoHS 狀態 — Non-compliant (legacy PQFP, non-LEAD-FREE process)
生命週期狀態 — Obsolete / last-time-buy per Altera PCN

資料表與資源

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