EP20K100QI240-2V vs EP20K100QC240-2 比較

詳細並排比較 EP20K100QI240-2V 由 Altera 與 EP20K100QC240-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP20K100QI240-2V EP20K100QI240-2V - FPGA APEX 20K 100K Gates | Altera

EP20K100QI240-2V - FPGA APEX 20K 100K Gates | Altera

EP20K100QI240-2V Obsolete

規格比較

參數 EP20K100QI240-2V EP20K100QC240-2
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Product Family APEX 20K —
Product Type Field Programmable Gate Array (FPGA) —
Total Gates 100K Gates —
Logic Elements/Cells 4,160 Cells —
Total RAM Bits 53,248 bits 53248
Number of User I/O 189 I/O lines —
Dedicated Inputs 4 dedicated inputs —
Maximum Internal Frequency 200 MHz 200 MHz
Process Technology 0.22 um CMOS —
Core Supply Voltage 2.5 V —
Operating Supply Voltage Range 2.375 V to 2.625 V —
封裝 / 外殼 240-Pin PQFP / 240-BFQFP 240-BFQFP (PQFP-240)
腳位數 240 —
安裝類型 Surface Mount Surface Mount
Architecture MultiCore with LUT logic, product-term logic, and embedded memory —
工作溫度範圍 [DATA_NEEDED: operating temperature range in degrees C] 0°C to 85°C (TJ)
RoHS 狀態 [DATA_NEEDED: RoHS status] Unknown
Series — APEX-20K
Device Type — Field Programmable Gate Array (FPGA)
Number of Logic Elements/Cells — 4160
Number of LABs/CLBs — 416
Number of User I/Os — 189
Typical Gate Count — 100000
Maximum System Gates — 263000
工作電源電壓 — 2.375 V to 2.625 V (2.5 V nominal)
Propagation Delay — 3 ns
Number of Pins / Terminals — 240
Terminal Pitch — 0.5 mm
Technology / Process — CMOS, 0.22 µm
Speed Grade — -2

資料表與資源

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