EP20K200CB356C8N vs EP20K200EBC356-2 比較
詳細並排比較 EP20K200CB356C8N 由 Altera 與 EP20K200EBC356-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K200CB356C8N | EP20K200EBC356-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20K (APEX 20KE enhancement) |
| Series | EP20K200 | APEX 20KE |
| Device Type | SRAM-based LUT FPGA | — |
| System Gates | 200,000 | — |
| Logic Elements (Cells) | 8,320 | — |
| Maximum Internal Frequency | 301.21 MHz | — |
| Process Technology | 0.15 um CMOS | — |
| Propagation Delay (tpd) | 1.78 ns | — |
| Nominal Core Supply Voltage | 1.8 V | — |
| Core Supply Voltage Range | 1.71 V to 1.89 V | — |
| Number of User I/O Pins | 263 | — |
| Number of Dedicated Inputs | 4 | — |
| Total Macrocells / Output Functions | 263 | — |
| Embedded Memory Bits | 106,496 bits | — |
| Number of PLLs | 4 | 4 embedded PLLs |
| MultiVolt I/O Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Differential Signaling | LVDS | — |
| Configuration Interface | Serial / JTAG (IEEE 1149.1) | — |
| 封裝 | 356-ball LBGA | — |
| Operating Temperature (commercial "C") | 0 C to +85 C (TJ) | — |
| Terminal Finish ("N") | Lead-free / Pb-free | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | — |
| 濕度敏感等級 (MSL) | [DATA_NEEDED: MSL rating] | — |
| Typical Gates | — | 200,000 |
| Maximum Logic Elements | — | 8320 |
| Macros / Logic Cells | — | 832 |
| Maximum Flip-Flops | — | 13,824 |
| Embedded RAM | — | 53,248 bits |
| User I/Os | — | 271 |
| Number of Terminals / Pins | — | 356 (LBGA) |
| Propagation Delay | — | 2.5 ns |
| 供應電壓 | — | 2.5 V (core) |
| 工作溫度 | — | 0 C to 85 C (commercial) |
| Logic Family | — | CMOS |
| Number of DDR Interfaces | — | 4 |
| Package Type | — | 356-LBGA (EBC suffix) |
| 安裝類型 | — | Surface Mount (BGA) |
| Speed Grade | — | -2 |
| Compliance | — | RoHS status [DATA_NEEDED: RoHS] |