EP20K200CF672C8ES vs EP20K400CF672C8ES 比較
詳細並排比較 EP20K200CF672C8ES 由 Intel 與 EP20K400CF672C8ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K200CF672C8ES | EP20K400CF672C8ES |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20KC |
| Maximum Logic Elements | 8,320 | — |
| Typical Gates | 200,000 system gates | — |
| Maximum User I/O Pins | 1,064 | — |
| Embedded RAM Bits | 212,992 bits | — |
| 封裝 | 672-ball FineLine BGA | 672-BGA FineLine (FC-FBGA / S-PBGA-B672) |
| Speed Grade | C8 (8 ns pin-to-pin) | — |
| 工作溫度 | 0C to +85C (commercial) | 0°C to 85°C (Commercial) |
| Core Voltage | 1.8 V | — |
| Configuration Method | SRAM, requires external PROM | — |
| Process Technology | [DATA_NEEDED: process node] | 0.15 µm CMOS |
| 安裝類型 | Surface Mount (BGA) | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | [DATA_NEEDED: not stated in verified data] |
| Status Suffix | ES (Engineering Sample) | — |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL | — |
| Logic Element Architecture | 4-input LUT with dedicated carry/cascade | — |
| Embedded Memory Type | RAM / ROM / CAM blocks | — |
| Series | — | EP20K400 |
| Logic Cells / Macros | — | 16,640 |
| System Gates (typical) | — | 400,000 |
| System Gates (maximum) | — | 212,992 [DATA_NEEDED: confirm datasheet interpretation] |
| Maximum User I/O | — | 488 (per Globalspec) / 484 (per Microchip USA) [DATA_NEEDED: confirm canonical value] |
| Bidirectional I/O | — | 484 |
| Propagation Delay | — | 2.5 ns |
| Maximum Internal Frequency | — | 301.21 MHz |
| Nominal Supply Voltage | — | 1.8 V |
| Supply Voltage Range | — | 1.71 V to 1.89 V |
| Logic Family | — | CMOS |
| Architecture | — | MultiCore™ (LUT + Embedded System Block) |
| Programming Method | — | JTAG / in-system via configuration memory |