EP20K200CQ240C8ES vs EP20K100CQ240C8ES 比較
詳細並排比較 EP20K200CQ240C8ES 由 Altera 與 EP20K100CQ240C8ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K200CQ240C8ES - 200K APEX 20KC FPGA, 240-PQFP | Altera (Intel PSG)
EP20K200CQ240C8ES Obsolete規格比較
| 參數 | EP20K200CQ240C8ES | EP20K100CQ240C8ES |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Device Logic Elements | 8,320 cells | — |
| Typical Gates | 200,000 | — |
| Embedded Memory | 106,496 bits | — |
| User I/O Count | 168 | — |
| Maximum Internal Clock Frequency | 301.21 MHz | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.15 µm CMOS | — |
| 封裝 | 240-BFQFP (PQFP) | — |
| 腳位數 | 240 | — |
| 工作溫度 | [DATA_NEEDED: Operating temperature range] | — |
| Speed Grade | C8 | — |
| Device Variant Suffix | ES (engineering sample) | — |
| PLLs | 4 | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Unknown - not confirmed in scraped listing |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Product Family | — | Intel/Altera EP20K series FPGA family |
| Number of Logic Elements / Cells | — | 4,160 |
| Total RAM Bits | — | 53,248 bits |
| Number of User I/O | — | 189 |
| 封裝 / 外殼 | — | 240-BFQFP / QFP-240 |
| Package Type | — | Quad Flat Package |
| Packaging | — | Tray |
| Ordering/ Speed Grade Suffix | — | C8ES |
| Stock Quantity | — | 4,816 pieces per Heisener listing |
| Lead Time | — | To Be Confirmed |
| Unit Price | — | Request a Quote |
| Minimum Operating Temperature | — | [DATA_NEEDED: minimum operating temperature] |
| Maximum Operating Temperature | — | [DATA_NEEDED: maximum operating temperature] |
| Core / I/O Supply Voltage | — | [DATA_NEEDED: VCCINT and VCCIO voltage] |
| Supported I/O Standards | — | [DATA_NEEDED: supported I/O standards] |
| Differential I/O Pairs | — | [DATA_NEEDED: number of differential I/O pairs] |
| Configuration Schemes | — | [DATA_NEEDED: supported configuration schemes] |