EP20K200EBC356-1N vs EP20K200EBC356-1 比較
詳細並排比較 EP20K200EBC356-1N 由 Intel 與 EP20K200EBC356-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K200EBC356-1N | EP20K200EBC356-1 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | APEX 20KE | APEX 20K (APEX 20KE) |
| Series | APEX-20KE | — |
| Logic Elements / Cells | 8,320 | 8,320 |
| Typical Gates | 200,000 | — |
| Number of Macrocells | 832 | — |
| User I/Os | 271 | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Internal Frequency (max) | 367 MHz | — |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V (nominal 1.8 V) | — |
| I/O Supply Voltage | MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V | — |
| 封裝 | 356-BGA (LBGA, 35 x 35 mm) | 356-ball LBGA (35 x 35 mm) |
| 工作溫度 | 0 C to +85 C (commercial) | 0 °C to 85 °C (Commercial) |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| MSL 等級 | 3 (168 hours) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not stated in verified sources] |
| Logic Family / Architecture | CMOS, MultiCore (LUT + embedded memory) | — |
| Configuration Method | SRAM-based, in-system programmable | JTAG (ByteBlaster / MasterBlaster), passive serial |
| System Gates | — | 200,000 |
| Maximum User I/Os | — | 277 |
| Core Voltage | — | 1.8 V (1.71 V to 1.89 V) |
| Internal Performance | — | Up to 367 MHz |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| On-chip Memory | — | Embedded System Blocks (ESB / SRAM) |
| Development Software | — | Altera Quartus II |
| 生命週期狀態 | — | Obsolete / EOL |