EP20K400CF672C7ES vs EP20K400CF672C-8 比較

詳細並排比較 EP20K400CF672C7ES 由 Altera 與 EP20K400CF672C-8 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K400CF672C7ES EP20K400CF672C-8
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX 20KC APEX 20K
Series EP20K400 —
Device Type Loadable PLD / FPGA —
Logic Elements (Cells) 16,640 —
System Gates 400,000 —
Embedded Memory (Bits) 212,992 —
Total RAM Bits 212,992 —
Maximum User I/O 488 488
I/O Lines 484 —
Input Lines 488 —
Number of PLLs 4 —
Maximum Internal Clock Frequency 375.94 MHz —
Propagation Delay 1.4 ns —
Process Technology 0.18 um CMOS 0.15 µm all-layer copper CMOS
Core Voltage 1.8 V —
MultiVolt I/O 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Speed Grade C7 (commercial, -7) -8
工作溫度 0C to +85C (commercial) —
Package Type 672-ball FineLine BGA PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch)
Package Code FC-FBGA-B672 —
Ball Pitch 1.000 mm —
安裝類型 Surface Mount Surface Mount (BGA)
RoHS 狀態 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Logic Elements — 16,640
Typical Gates — 400,000
Macros — 1,664
Number of I/O Banks — [DATA_NEEDED: number of I/O banks]
Core Voltage (VCCINT) — 1.8 V nominal (1.71 V to 1.89 V)
I/O Voltage (VCCIO) — [DATA_NEEDED: VCCIO options]
Pin-to-Pin Delay (tPD) — 1.78 ns (speed grade -8)
Temperature Grade (C) — Commercial, 0 °C to 85 °C
Embedded Memory Type — ESB (RAM / ROM / CAM)
Configuration Interface — JTAG (IEEE 1149.1), Passive Serial, Passive Parallel
JTAG Support — Yes (IEEE 1149.1 boundary-scan)
MSL 等級 — [DATA_NEEDED: MSL level]

資料表與資源

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