EP20K400FC672-2 vs EP20K400FI672-2N 比較

詳細並排比較 EP20K400FC672-2 由 Intel 與 EP20K400FI672-2N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K400FC672-2 EP20K400FI672-2N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Series APEX-20K —
Family APEX-20K (MultiCore) APEX 20K
Logic Elements / Cells 16640 16,640
Number of Macrocells 1664 —
Number of Logic Blocks [DATA_NEEDED: LAB count] —
Number of Gates 400000 —
Embedded Memory (Bits) 212992 —
Maximum User I/O 502 488
Number of I/O Banks [DATA_NEEDED: I/O bank count] —
Operating Frequency (Max) 200 MHz —
Propagation Delay (tpd) 2.5 ns —
Core Supply Voltage 2.5 V —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
工作溫度 0°C to +85°C (Commercial) Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant]
封裝 672-ball FC-FBGA (BBGA) 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA)
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: RoHS status] Compliant (lead-free)
Speed Grade -2 -2
Typical Gates — 400,000
Embedded Memory Bits — 212,992 bits
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count per family datasheet]
Core Voltage — 2.5 V
Maximum Frequency — 200 MHz
Package Body Size — 27 x 27 mm
Terminal Pitch — 1.0 mm
Propagation Delay — 3.1 ns
濕度敏感等級 (MSL) — 3
Peak Reflow Temperature — 220 °C
Configuration Modes — PS, PPS, PPA, JTAG
Supported I/O Standards — LVTTL, LVCMOS, SSTL, HSTL

資料表與資源

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