EP20K400FC672-3 vs EP20K400FI672-2 比較
詳細並排比較 EP20K400FC672-3 由 Altera 與 EP20K400FI672-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 Obsolete規格比較
| 參數 | EP20K400FC672-3 | EP20K400FI672-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20K | APEX-20K |
| Device Logic Elements | 16,640 cells | — |
| Typical Gate Count | 400,000 system gates | — |
| Maximum User I/Os | 502 | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Internal Performance | 167 MHz | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| Logic Family | CMOS, SRAM-based | — |
| 封裝 | 672-pin FC-FBGA | — |
| Package Code | BGA | — |
| Number of Terminals | 672 | — |
| Terminal Form | Ball (BGA) | — |
| Speed Grade | -3 (commercial fastest) | — |
| 工作溫度 | 0 °C to 85 °C | 0 °C to +85 °C (Commercial) |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming Method | SRAM, JTAG (ByteBlaster) | — |
| 生命週期狀態 | Obsolete / Legacy | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Lead-free / RoHS Compliant |
| Logic Elements | — | 16640 |
| Maximum Gates | — | 400,000 gates |
| User I/Os | — | 502 |
| Embedded Memory Bits | — | 212992 |
| Number of Macros | — | 1664 |
| Maximum Internal Frequency | — | 200 MHz |
| Package Type | — | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) |
| PLLs (Phase-Locked Loops) | — | 4 |
| Configuration Modes | — | JTAG, Passive Serial, Passive Parallel |