EP20K400GC655-1 vs EP20K400GC655-2V 比較
詳細並排比較 EP20K400GC655-1 由 Intel 與 EP20K400GC655-2V 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 Obsolete規格比較
| 參數 | EP20K400GC655-1 | EP20K400GC655-2V |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | APEX 20K | APEX 20KC (1.8 V, LVDS) |
| Series | EP20K400 | APEX-20KC |
| Logic Elements | 16,640 | 16,640 |
| Maximum Gates | 1,052,000 | — |
| Typical Gates | 400,000 | — |
| Embedded System Blocks (ESBs) | 4 | — |
| Total RAM Bits | 212,992 | 212,992 |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 6 | — |
| Process Technology | 0.22 µm CMOS | CMOS, 0.18 um |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | 3.000 ns |
| 封裝 | 655-pin CPGA (Ceramic Pin Grid Array) | 655-CPGA (62.48 x 62.48 mm) |
| 腳位數 | 655 | — |
| 安裝類型 | Through-Hole | Through-hole (CPGA) |
| 工作溫度 | 0 °C to +85 °C (commercial) | [DATA_NEEDED: temperature grade] |
| Configuration Modes | Passive Serial, Passive Parallel Async, Passive Parallel Sync | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| RoHS 狀態 | Non-compliant (contains lead in ceramic package) | unknown |
| System Gates | — | ~400,000 (typical marketing figure) |
| Number of I/O | — | [DATA_NEEDED: I/O count] |
| Core Voltage (VCCINT) | — | 2.375 V to 2.625 V (nominal 2.5 V) |
| LVDS Support | — | Yes |
| Package Type | — | Ceramic Pin Grid Array, through-hole |
| Speed Grade | — | -2 |
| Lead-Free | — | unknown |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |