EP20K400GC655-2N vs EP20K400GC655-1V 比較
詳細並排比較 EP20K400GC655-2N 由 Altera 與 EP20K400GC655-1V 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GC655-2N | EP20K400GC655-1V |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KE |
| Number of Logic Elements | 16640 | — |
| Number of Logic Cells | 16640 | — |
| Total System Gates | 400000 | — |
| Total RAM Bits | 212992 | — |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage (VCCIO) | 2.5 V (LVDS-capable) | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Maximum Operating Frequency | 200 MHz | — |
| Propagation Delay (Tpd) | 3.1 ns | — |
| 封裝 / 外殼 | 655-BCPGA (Ceramic Pin Grid Array) | — |
| Supplier Device Package | 655-CPGA, 62.48 x 62.48 mm | — |
| 工作溫度 | Industrial (per Altera part-number -N suffix) | — |
| 安裝類型 | Through-Hole (CPGA, socket-compatible) | — |
| LVDS Support | Yes | Yes |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Configuration Method | JTAG / Passive Serial | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Logic Elements | — | 16,640 |
| Typical Gate Count | — | 400,000 gates |
| Embedded Memory | — | 212,992 bits |
| Maximum User I/O | — | 496 |
| Dedicated Inputs | — | 6 |
| 封裝 | — | CBGA-655 (Ceramic Ball Grid Array) |
| Total Terminals | — | 655 |
| Supply Voltage (Core) | — | 2.375 V to 2.625 V (nominal 2.5 V) |
| Propagation Delay | — | 2.5 ns |
| Maximum Internal Frequency | — | 250 MHz (-1V speed grade) |
| Moisture Sensitivity Level | — | MSL 1 |
| Peak Reflow Temperature | — | 220 °C |
| Qualification | — | Not Qualified |
| Programming Interface | — | IEEE 1532 / JTAG |