EP20K400GC655-2V vs EP20K400GC655-1 比較
詳細並排比較 EP20K400GC655-2V 由 Altera 與 EP20K400GC655-1 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 Obsolete規格比較
| 參數 | EP20K400GC655-2V | EP20K400GC655-1 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | APEX-20KC | EP20K400 |
| Family | APEX 20KC (1.8 V, LVDS) | APEX 20K |
| Logic Elements | 16,640 | 16,640 |
| Total RAM Bits | 212,992 | 212,992 |
| System Gates | ~400,000 (typical marketing figure) | — |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 3.000 ns | 2.5 ns |
| Process Technology | CMOS, 0.18 um | 0.22 µm CMOS |
| LVDS Support | Yes | — |
| 封裝 | 655-CPGA (62.48 x 62.48 mm) | 655-pin CPGA (Ceramic Pin Grid Array) |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| 安裝類型 | Through-hole (CPGA) | Through-Hole |
| Speed Grade | -2 | — |
| 工作溫度 | [DATA_NEEDED: temperature grade] | 0 °C to +85 °C (commercial) |
| RoHS 狀態 | unknown | Non-compliant (contains lead in ceramic package) |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 250 MHz |
| 腳位數 | — | 655 |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |