EP20K400GC655-2V vs EP20K400GI655-3V 比較
詳細並排比較 EP20K400GC655-2V 由 Altera 與 EP20K400GI655-3V 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP20K400GI655-3V - APEX 20K 400K-Gate FPGA, 16K LE, 655-Pin PGA | Altera (Intel)
EP20K400GI655-3V Obsolete規格比較
| 參數 | EP20K400GC655-2V | EP20K400GI655-3V |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | APEX-20KC | APEX 20K |
| Family | APEX 20KC (1.8 V, LVDS) | — |
| Logic Elements | 16,640 | 16,640 |
| Total RAM Bits | 212,992 | — |
| System Gates | ~400,000 (typical marketing figure) | — |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 3.000 ns | — |
| Process Technology | CMOS, 0.18 um | — |
| LVDS Support | Yes | — |
| 封裝 | 655-CPGA (62.48 x 62.48 mm) | 655-pin SPGA (Staggered PGA), 47 x 47 mm |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| 安裝類型 | Through-hole (CPGA) | Through-Hole (Pin Grid Array) |
| Speed Grade | -2 | — |
| 工作溫度 | [DATA_NEEDED: temperature grade] | -40 °C to +85 °C (industrial) |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Device Family | — | EP20K400 |
| Typical Gate Count | — | 400,000 gates |
| Maximum User I/O | — | 496 |
| Dedicated Inputs | — | 6 |
| Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| Total Embedded RAM | — | [DATA_NEEDED: total RAM bits] |
| Technology | — | CMOS (0.18 µm process) |
| Maximum Internal Clock Frequency | — | 714.2 MHz |
| Supply Voltage VCCINT | — | 2.5 V |
| I/O Supply Voltage VCCIO | — | 2.5 V or 3.3 V |
| 濕度敏感等級 (MSL) | — | 1 |
| Qualification | — | Not Qualified |
| Configuration Interface | — | IEEE 1149.1 JTAG + serial / parallel passive |