EP20K400GI655-1X vs EP20K400GI655-1V 比較
詳細並排比較 EP20K400GI655-1X 由 Altera 與 EP20K400GI655-1V 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X Obsolete
規格比較
| 參數 | EP20K400GI655-1X | EP20K400GI655-1V |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | APEX 20K | APEX 20K |
| Device | EP20K400 | — |
| Logic Elements | 16640 | 16,640 |
| Number of Terminals | 655 | — |
| User I/O Lines | 502 | — |
| Dedicated Inputs | 4 | 4 |
| Package Type | Ceramic Pin Grid Array (CPGA) | CBGA-655 (Ceramic Ball Grid Array) |
| Package Code (JESD-30) | S-CPGA-P655 | S-CPGA-P655 |
| Package Equivalence Code | SPGA655,47X47 | SPGA655, 47x47 |
| Package Body Material | CERAMIC (metal-sealed co-fired) | Ceramic |
| Speed Grade | -1 | — |
| Propagation Delay | 2.5 ns (typical for -1 grade) | 2.5 ns |
| Process Technology | CMOS, SRAM-based configuration | CMOS |
| 濕度敏感等級 (MSL) | 1 | — |
| Peak Reflow Temperature | 220 C | — |
| 工作溫度 | -40 C to +85 C (industrial) | [DATA_NEEDED: industrial vs military grade] |
| 安裝類型 | Through-Hole (PGA) | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED] |
| Typical Gates | — | 400,000 |
| Maximum User I/O | — | 502 |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 2.5 V / 3.3 V |
| Configuration | — | In-system programmable via JTAG |
| Boundary Scan | — | IEEE 1149.1 JTAG |
| MSL 等級 | — | 1 |