EP20K400GI655-2 vs EP20K400GC655-2 比較
詳細並排比較 EP20K400GI655-2 由 Altera 與 EP20K400GC655-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GI655-2 | EP20K400GC655-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Manufacturer | Altera Corporation | — |
| Series | APEX 20K (EP20K400) | APEX-20KC |
| Device Type | Field Programmable Gate Array (FPGA) | FPGA (Field Programmable Gate Array) |
| Typical Gate Count | 400,000 gates | — |
| Logic Elements (LE) | 16,640 | — |
| Maximum User I/O | 496 | — |
| Dedicated Inputs | 6 | — |
| Number of Terminals | 655 | — |
| 封裝 | SPGA-655 (47 mm x 47 mm) | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Propagation Delay | 3.1 ns (typical) | — |
| Technology | CMOS SRAM | — |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| 安裝類型 | Through-Hole / Socket | Through-Hole (CPGA) |
| Moisture Sensitivity Level | 1 (per Altera family) | — |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | — |
| Embedded Memory | Embedded System Blocks (ESBs) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| 生命週期狀態 | Obsolete (legacy Altera APEX 20K family) | — |
| Family | — | APEX 20K |
| System Gates | — | 400,000 |
| Logic Cells / Elements | — | 16,640 |
| Total RAM Bits | — | 212,992 |
| Maximum Internal Frequency | — | 200 MHz |
| Speed Grade | — | -2 |
| Process Technology | — | 0.22 µm CMOS |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 1.71 V to 1.89 V (MultiVolt) |
| LVDS Support | — | Yes |
| PLLs | — | 4 |
| 腳位數 | — | 655 |
| Package Type | — | 655-BCPGA (CPGA-655) |
| Package Dimensions | — | 62.48 x 62.48 mm |