EP20K400GI655-2 vs EP20K400GI655-2V 比較
詳細並排比較 EP20K400GI655-2 由 Altera 與 EP20K400GI655-2V 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GI655-2 | EP20K400GI655-2V |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Manufacturer | Altera Corporation | — |
| Series | APEX 20K (EP20K400) | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Typical Gate Count | 400,000 gates | — |
| Logic Elements (LE) | 16,640 | — |
| Maximum User I/O | 496 | — |
| Dedicated Inputs | 6 | 6 |
| Number of Terminals | 655 | — |
| 封裝 | SPGA-655 (47 mm x 47 mm) | SPGA-655 (ceramic, 47 x 47 mm) |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Propagation Delay | 3.1 ns (typical) | 3.0 ns to 3.1 ns |
| Technology | CMOS SRAM | — |
| 工作溫度 | -40C to +85C (industrial) | Industrial (per -2V speed grade) |
| 安裝類型 | Through-Hole / Socket | — |
| Moisture Sensitivity Level | 1 (per Altera family) | — |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | — |
| Embedded Memory | Embedded System Blocks (ESBs) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic SPGA, contains lead) |
| 生命週期狀態 | Obsolete (legacy Altera APEX 20K family) | — |
| Family | — | APEX 20K |
| Maximum Gates | — | 400,000 |
| Logic Elements | — | 16,640 |
| Embedded RAM Bits | — | 212,992 |
| User I/O Pins | — | 496 |
| Package Equivalence Code | — | SPGA655,47X47 |
| Process Technology | — | 0.18 µm CMOS |
| Core Supply Voltage | — | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage | — | 3.3 V |
| 濕度敏感等級 (MSL) | — | 1 |
| Package Body Material | — | Ceramic |