EP20K400GI655-3 vs EP20K400GI655-2V 比較
詳細並排比較 EP20K400GI655-3 由 Altera 與 EP20K400GI655-2V 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GI655-3 | EP20K400GI655-2V |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KE | APEX 20K |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 (maximum) | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 4 | 6 |
| Number of Terminals | 655 | — |
| 封裝 | 655-Pin PGA (Plastic/CPGA, square) | SPGA-655 (ceramic, 47 x 47 mm) |
| JESD-30 Code | S-CPGA-P655 | — |
| Package Shape | Square | — |
| Form of Terminal | PIN/PEG (through-hole) | — |
| 安裝類型 | Through-Hole (Socket) | — |
| Process Technology | CMOS, 2.5V core | 0.18 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) | 3.3 V |
| 工作溫度 | 0°C to 70°C (Industrial I grade) | Industrial (per -2V speed grade) |
| Speed Grade | -3 (slowest of the EP20K400 family) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG | — |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic SPGA, contains lead) |
| Maximum Gates | — | 400,000 |
| Logic Elements | — | 16,640 |
| Embedded RAM Bits | — | 212,992 |
| User I/O Pins | — | 496 |
| Package Equivalence Code | — | SPGA655,47X47 |
| Propagation Delay | — | 3.0 ns to 3.1 ns |
| 濕度敏感等級 (MSL) | — | 1 |
| Package Body Material | — | Ceramic |