EP20K400GI655-3 vs EP20K400GI655-2X 比較
詳細並排比較 EP20K400GI655-3 由 Altera 與 EP20K400GI655-2X 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GI655-3 | EP20K400GI655-2X |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KE | APEX-20K (loadable PLD / FPGA) |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 (maximum) | 400,000 |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 4 | — |
| Number of Terminals | 655 | — |
| 封裝 | 655-Pin PGA (Plastic/CPGA, square) | 655-ball FineLine BGA (SPGA655, 47x47 mm) |
| JESD-30 Code | S-CPGA-P655 | — |
| Package Shape | Square | — |
| Form of Terminal | PIN/PEG (through-hole) | — |
| 安裝類型 | Through-Hole (Socket) | — |
| Process Technology | CMOS, 2.5V core | CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) | — |
| 工作溫度 | 0°C to 70°C (Industrial I grade) | — |
| Speed Grade | -3 (slowest of the EP20K400 family) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG | — |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Series | — | APEX-20K |
| Logic Elements (LEs) | — | 16,640 |
| Total I/O Lines | — | 496 (bidirectional) + 4 (dedicated inputs) |
| Embedded Memory (bits) | — | 212,992 |
| Nominal Core Supply Voltage | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| I/O Supply Voltages | — | 2.5 V / 3.3 V |
| Propagation Delay (typical, -2 grade) | — | 3.1 ns |
| Package Code | — | SPGA655, 47x47 |
| Surface Mount | — | Yes (BGA) |
| 濕度敏感等級 (MSL) | — | 1 |
| Operating Temperature (industrial -X grade) | — | -40C to +85C (industrial) |
| Qualification | — | Not Qualified (per distributor listing) |
| JTAG Support | — | IEEE 1149.1 boundary-scan / programming |