EP20K400GI655-3X vs EP20K400GI655-3 比較

詳細並排比較 EP20K400GI655-3X 由 Intel 與 EP20K400GI655-3 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K400GI655-3X EP20K400GI655-3
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Unknown Obsolete
Product Type Field Programmable Gate Array —
Device Family APEX 20K —
Logic Elements/Cells 16,640 —
Technology CMOS —
Terminal Count 655 —
Package Type SPGA —
Package Designation SPGA655 —
Package Dimensions 47 mm x 47 mm —
Power Supply 2.5 V —
Power Supply Option 2.5/3.3 V —
安裝類型 [DATA_NEEDED: mounting type] Through-Hole (Socket)
工作溫度 [DATA_NEEDED: operating temperature] 0°C to 70°C (Industrial I grade)
I/O Count [DATA_NEEDED: I/O count] —
Embedded Memory [DATA_NEEDED: embedded memory capacity] Dual-port RAM via Embedded System Blocks (ESBs)
Configuration Method [DATA_NEEDED: configuration method] —
RoHS 狀態 unknown [DATA_NEEDED: RoHS status]
REACH Status unknown —
AEC-Q100 Qualification unknown —
Family — APEX 20KE
Logic Elements / Cells — 16,640
System Gates — 400,000 (maximum)
Maximum User I/O — 502
Dedicated Inputs — 4
Number of Terminals — 655
封裝 — 655-Pin PGA (Plastic/CPGA, square)
JESD-30 Code — S-CPGA-P655
Package Shape — Square
Form of Terminal — PIN/PEG (through-hole)
Process Technology — CMOS, 2.5V core
Core Supply Voltage — 2.5 V
I/O Supply Voltage — 2.5 V or 3.3 V (MultiVolt I/O)
Speed Grade — -3 (slowest of the EP20K400 family)
Configuration Modes — Passive Serial, Passive Parallel Asynchronous, JTAG
JTAG / Boundary Scan — IEEE 1149.1 compliant

資料表與資源

瀏覽所有產品 建立 BOM 索取報價