EP20K600CF672-1X vs EP20K600CF672-2 比較

詳細並排比較 EP20K600CF672-1X 由 Intel 與 EP20K600CF672-2 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K600CF672-1X EP20K600CF672-2
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Obsolete
Series APEX 20KC APEX 20KC
Device Family APEX 20KC MultiCore FPGA APEX 20KC PLD
Maximum Typical Gates 600,000 —
Logic Elements 31,104 (per Altera APEX 20KC datasheet family) 30,720
Embedded System Blocks (ESBs) up to 256 —
Embedded Memory (max bits) [DATA_NEEDED: ESB RAM bits] —
PLLs 4 —
Maximum User I/O [DATA_NEEDED: max user I/O count] —
封裝 672-ball BGA (CF672), 1.27 mm pitch —
Speed Grade -1 (industrial speed grade, X = lead-free) -2
Process Technology 0.18 um SRAM CMOS 0.18 um CMOS
Configuration Method SRAM, JTAG (IEEE 1149.1), EPC passive serial —
供應電壓 [DATA_NEEDED: VCCINT/VCCIO] —
工作溫度 [DATA_NEEDED: industrial temp range] 0 C to +60 C (TJ, per Alibaba supplier listing)
安裝類型 Surface Mount (BGA) Surface Mount
MSL 等級 [DATA_NEEDED: MSL rating] —
RoHS 狀態 Compliant (per Alibaba distributor listing: "RoHS Compliant") [DATA_NEEDED: rohs_status]
Manufacturer — Intel / Altera
Gate Count (typical) — 600,000 gates
Embedded RAM (approx.) — 311,232 bits
Package Type — 672-ball FineLine BGA (FCBGA)
Configuration Mode — Enhanced Configuration (EPC)
Number of PLLs — 4
I/O Standards — LVTTL, LVCMOS, and others per datasheet
Boundary Scan — IEEE 1149.1 (JTAG)
生命週期狀態 — Obsolete / last-time-buy

資料表與資源

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