EP20K600CF672 vs EP20K600CEF672C7 比較
詳細並排比較 EP20K600CF672 由 Intel 與 EP20K600CEF672C7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP20K600CF672 - 600K APEX 20KC FPGA, 672-BGA | Intel
EP20K600CF672 [data_needed: lifecycle status]
規格比較
| 參數 | EP20K600CF672 | EP20K600CEF672C7 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | [DATA NEEDED: Lifecycle Status] | Obsolete |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Product Family | APEX-20KC | — |
| Manufacturer | Altera / Intel | Intel (formerly Altera) |
| User I/O Lines | 508 I/O | — |
| Logic Elements | [DATA_NEEDED: logic element count] | — |
| Propagation Delay | 1.48 ns for supplied EP20K600CF672C9N/C8N references | 1.48 ns (typ) |
| Device Type Listed by Supplied References | SPLD | — |
| Process Technology | 0.15 um all-layer copper-metal process for supplied family references | 0.15 µm CMOS, all-layer copper |
| Performance Claim | Up to 35% faster than APEX 20KE devices | — |
| Package Type | 672-ball BGA, FCBGA | — |
| Package Dimensions | 45 mm x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | 0 C to 85 C for supplied EP20K600CF672C9N/C8N references | 0 °C to +85 °C (commercial) |
| Configuration Device Type | Enhanced Configuration (EPC) device | — |
| Core Voltage | [DATA_NEEDED: core supply voltage] | — |
| I/O Voltage | [DATA_NEEDED: I/O supply voltage] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory type and capacity] | — |
| Embedded Memory | [DATA_NEEDED: embedded memory capacity] | EAB blocks (dual-port RAM with byte enables) |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| AEC-Q100 Status | unknown | — |
| Series | — | APEX 20KC |
| Family | — | APEX 20KC (Enhanced Configuration) |
| Device Type | — | FPGA / Loadable PLD |
| Logic Elements / Cells | — | 24,320 |
| Gate Count (typical) | — | 600,000 gates |
| Maximum Operating Frequency | — | 375.94 MHz |
| User I/Os | — | 488 |
| Core Supply Voltage | — | 1.8 V |
| 封裝 | — | 672-ball FineLine BGA (FC-FBGA) |
| Package Code | — | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Configuration | — | SRAM-based, serial or parallel (EPC) |
| LVDS Support | — | True-LVDS channels integrated |
| MultiVolt I/O | — | 1.8 V, 2.5 V, 3.3 V interfaces |
| External Memory Interface | — | DDR SDRAM, QDR SRAM |
| JTAG Support | — | IEEE 1149.1 boundary-scan |