EP20K600CF672C-9 vs EP20K600CB672C7 比較

詳細並排比較 EP20K600CF672C-9 由 Altera 與 EP20K600CB672C7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K600CF672C-9 EP20K600CB672C7
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Device Type FPGA (APEX 20KC family, complex PLD) FPGA / Programmable Logic Device (PLD)
Typical Gate Count 600,000 gates —
Logic Elements (LEs) [DATA_NEEDED: logic element count] —
Embedded System Blocks (ESBs) [DATA_NEEDED: ESB count and total RAM bits] —
User I/Os 488 pins 488
PLLs 4 —
封裝 672-ball FBGA (45 x 45 mm, 1.27 mm pitch) 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch)
腳位數 672 —
Core Supply Voltage (VCCINT) 1.8 V —
I/O Supply Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) —
Propagation Delay 1.48 ns 1.48 ns
工作溫度 0 °C to +85 °C (commercial) 0 °C to 85 °C (commercial)
Speed Grade -9 C7 (commercial, 0 °C to 85 °C)
Process Technology 0.15 µm all-layer copper interconnect 0.15 µm all-layer copper-metal CMOS
Configuration Interface Serial (EPC16 / EPC8 / EPC4 / EPC2 / EPC1) —
安裝類型 Surface Mount (BGA) —
RoHS 狀態 unknown Compliant
Family — APEX 20KC
Typical Gates — 600,000
Maximum System Gates — 1,053,840
Logic Elements — 30,960 (typical)
Embedded Memory — 311 kbits (EAB-based)
Core Voltage — 2.5 V
I/O Voltage Support — 1.8 V, 2.5 V, 3.3 V (MultiVolt I/O)
Number of PLLs — 4
Dual-Port RAM — Yes (4.5 ns access)
Supported I/O Standards — LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL, CTT
Configuration Method — EPC configuration devices / JTAG / passive serial

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