EP20K600CF672C-9 vs EP20K600CF672-3 比較

詳細並排比較 EP20K600CF672C-9 由 Altera 與 EP20K600CF672-3 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K600CF672C-9 EP20K600CF672-3
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Device Type FPGA (APEX 20KC family, complex PLD) —
Typical Gate Count 600,000 gates —
Logic Elements (LEs) [DATA_NEEDED: logic element count] —
Embedded System Blocks (ESBs) [DATA_NEEDED: ESB count and total RAM bits] —
User I/Os 488 pins —
PLLs 4 4
封裝 672-ball FBGA (45 x 45 mm, 1.27 mm pitch) 672-ball FineLine BGA
腳位數 672 —
Core Supply Voltage (VCCINT) 1.8 V —
I/O Supply Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) —
Propagation Delay 1.48 ns —
工作溫度 0 °C to +85 °C (commercial) [DATA_NEEDED: operating temperature range]
Speed Grade -9 -3
Process Technology 0.15 µm all-layer copper interconnect 0.18 µm CMOS
Configuration Interface Serial (EPC16 / EPC8 / EPC4 / EPC2 / EPC1) —
安裝類型 Surface Mount (BGA) Surface Mount
RoHS 狀態 unknown Lead-free / RoHS compliant (per Alibaba listing)
Family — APEX 20KC
Typical Gates — 600,000
Maximum System Gates — 2,432,000
Maximum Logic Elements — 2,432
Embedded System Memory — 311,040 bits (380 Kbits ESB)
User I/O Pins — 488
Maximum Internal Frequency — 180 MHz (per APEX 20K family datasheet)
Configuration Modes — PS, PPS, PPA, JTAG, EPC2/EPC16
I/O Standards Supported — LVTTL, LVCMOS, SSTL-2/3, HSTL, LVDS, PCI

資料表與資源

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