EP20K600CF672C6 vs EP20K600CF672C7N 比較
詳細並排比較 EP20K600CF672C6 由 Altera 與 EP20K600CF672C7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K600CF672C6 | EP20K600CF672C7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Typical Gate Count | 600,000 gates | — |
| Logic Elements (LEs) | 24,320 | — |
| Embedded System Blocks (ESBs) | 160 (each 2,048 bits) | — |
| Maximum Embedded RAM | 311,296 bits (311 kbit) | — |
| Maximum User I/O Pins | 508 | 488 |
| 封裝 | 672-ball FineLine BGA (CF672) | FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | -6 (C6) | C7 |
| 工作溫度 | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (Commercial) |
| Core Voltage | 1.8 V | 1.8 V |
| I/O Standards Supported | LVCMOS, LVTTL, HSTL, SSTL, GTL+ | — |
| Embedded PLLs | 4 | — |
| Process Technology | 0.18 µm CMOS, 6 metal layers | 0.15 µm all-layer copper-metal CMOS |
| Configuration Method | SRAM-based, JTAG, EPC16/EPC2 | — |
| RoHS 狀態 | Non-RoHS (legacy process) | unknown |
| Device Family | — | APEX 20KC |
| Maximum System Gates | — | 1,052,000 |
| Typical Gates | — | 600,000 |
| Logic Elements / Cells | — | 24,320 |
| Total Package Pins | — | 652 |
| Maximum Operating Frequency | — | 375.94 MHz |
| Propagation Delay | — | 1.48 ns |
| Architecture | — | MultiCore (LUT + Embedded System Memory) |
| Seated Height | — | 3.50 mm |
| 安裝類型 | — | Surface Mount (BGA) |