EP20K600CF672C7 vs EP20K600CEF672C7 比較

詳細並排比較 EP20K600CF672C7 由 Intel 與 EP20K600CEF672C7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K600CF672C7 EP20K600CEF672C7
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX-20KC APEX 20KC (Enhanced Configuration)
Device Type SPLD / FPGA FPGA / Loadable PLD
System Gates 600,000 —
Logic Cells 24,320 —
User I/O 508 —
封裝 672-ball FC-FBGA (27x27 mm) 672-ball FineLine BGA (FC-FBGA)
Ball Pitch 1.27 mm —
Core Voltage (VCCINT) 1.71 V to 1.89 V —
Process Technology 0.15 um CMOS, all-layer copper 0.15 µm CMOS, all-layer copper
Propagation Delay (typ.) 1.48 ns —
工作溫度 0C to 85C (commercial) 0 °C to +85 °C (commercial)
Speed Grade C7 —
Embedded Memory Dual-port RAM via ESBs EAB blocks (dual-port RAM with byte enables)
CAM Support Yes (ESB-based content-addressable memory) —
安裝類型 Surface Mount —
RoHS 狀態 Compliant [DATA_NEEDED: RoHS status]
Manufacturer — Intel (formerly Altera)
Series — APEX 20KC
Logic Elements / Cells — 24,320
Gate Count (typical) — 600,000 gates
Maximum Operating Frequency — 375.94 MHz
Propagation Delay — 1.48 ns (typ)
User I/Os — 488
Core Supply Voltage — 1.8 V
Package Code — BGA-652, 45 x 45 mm, 1.27 mm pitch
Configuration — SRAM-based, serial or parallel (EPC)
LVDS Support — True-LVDS channels integrated
MultiVolt I/O — 1.8 V, 2.5 V, 3.3 V interfaces
External Memory Interface — DDR SDRAM, QDR SRAM
JTAG Support — IEEE 1149.1 boundary-scan

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