EP20K600CF672C8N vs EP20K600CF672I-8ES 比較

詳細並排比較 EP20K600CF672C8N 由 Intel 與 EP20K600CF672I-8ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K600CF672C8N EP20K600CF672I-8ES
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 Obsolete
Device Type SPLD —
Product Type FPGA / programmable logic device —
Family APEX 20KC APEX 20KC
Nominal Gate Capacity 600K gates —
Logic Elements or Cells 24,320 —
Macros 2,432 —
User I/O Count 508 —
Package Terminals 652 pins —
封裝 BGA-652, 45 x 45 mm, 1.27 mm pitch 672-ball BGA (FineLine BGA, 1.27 mm pitch)
Package Description 672-pin FC-FBGA —
供應電壓 1.8 V —
Listed Frequency 301.21 MHz —
Propagation Delay 1.48 ns —
Fabrication Process 0.15 µm —
工作溫度 0°C to 85°C -40C to +100C (Industrial)
Interconnect Metal All-layer copper metal —
I/O Configuration 508 user I/O —
安裝類型 Surface mount —
RoHS 狀態 unknown Non-compliant (legacy Altera leaded BGA process)
REACH Status unknown —
AEC-Q100 Qualification unknown —
Configuration Method [DATA_NEEDED: configuration memory and programming method] —
Core Current [DATA_NEEDED: core supply current] —
I/O Bank Voltage [DATA_NEEDED: supported I/O voltage range] —
Junction Temperature [DATA_NEEDED: maximum junction temperature] —
熱阻 [DATA_NEEDED: junction-to-ambient thermal resistance] —
Logic Elements — 24,320
Typical Gates — 600,000 (ASIC-equivalent)
Embedded Memory Bits — 311,296
Maximum User I/O Pins — 508
Embedded PLLs — 4
Core Voltage — 1.8 V
I/O Standards Supported — LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+
Process Technology — 0.18 micron CMOS SRAM
Speed Grade — -8 (slower)
Configuration Modes — Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG
In-System Programmability — Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1)
MSL 等級 — [DATA_NEEDED: moisture sensitivity level]

資料表與資源

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