EP20K600CF672I-8ES vs EP20K600CF672C7N 比較
詳細並排比較 EP20K600CF672I-8ES 由 Altera 與 EP20K600CF672C7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K600CF672I-8ES - APEX 20KC 600K-Gate FPGA, 672-BGA | Intel / Altera
EP20K600CF672I-8ES Obsolete
規格比較
| 參數 | EP20K600CF672I-8ES | EP20K600CF672C7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | — |
| Logic Elements | 24,320 | — |
| Typical Gates | 600,000 (ASIC-equivalent) | 600,000 |
| Embedded Memory Bits | 311,296 | — |
| Maximum User I/O Pins | 508 | 488 |
| Embedded PLLs | 4 | — |
| Core Voltage | 1.8 V | 1.8 V |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ | — |
| Process Technology | 0.18 micron CMOS SRAM | 0.15 µm all-layer copper-metal CMOS |
| Speed Grade | -8 (slower) | C7 |
| 工作溫度 | -40C to +100C (Industrial) | 0 °C to +85 °C (Commercial) |
| 封裝 | 672-ball BGA (FineLine BGA, 1.27 mm pitch) | FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch |
| Configuration Modes | Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG | — |
| In-System Programmability | Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1) | — |
| RoHS 狀態 | Non-compliant (legacy Altera leaded BGA process) | unknown |
| MSL 等級 | [DATA_NEEDED: moisture sensitivity level] | — |
| Device Family | — | APEX 20KC |
| Maximum System Gates | — | 1,052,000 |
| Logic Elements / Cells | — | 24,320 |
| Total Package Pins | — | 652 |
| Maximum Operating Frequency | — | 375.94 MHz |
| Propagation Delay | — | 1.48 ns |
| Architecture | — | MultiCore (LUT + Embedded System Memory) |
| Seated Height | — | 3.50 mm |
| 安裝類型 | — | Surface Mount (BGA) |