EP20K600CF672I7N vs EP20K600CF672I8 比較
詳細並排比較 EP20K600CF672I7N 由 Intel 與 EP20K600CF672I8 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K600CF672I7N | EP20K600CF672I8 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Technology | 0.15 µm CMOS | — |
| Maximum System Gates | 600,000 | — |
| Logic Elements | 24,320 | — |
| Maximum User I/O Pins | 508 | — |
| Maximum Internal Frequency | 376 MHz | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Total Embedded RAM (max) | 311,296 bits | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | — |
| 封裝 | 672-ball FineLine BGA (FC-FBGA) | — |
| Ball Pitch | 1.0 mm | — |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | I7 (-40 °C to +100 °C industrial) | — |
| Propagation Delay (typical) | 1.6 ns | 1.48 ns |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | — |
| Lead-Free Finish (N suffix) | Yes | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Compliant per legacy product records |
| Device Type | — | SPLD / FPGA |
| Logic Elements / Cells | — | 24,320 |
| Macros (Logic Cells) | — | 2432 |
| Typical Gate Count | — | 600,000 gates |
| Embedded Memory | — | 311,296 bits |
| User I/Os | — | 488 to 508 |
| 腳位數 | — | 652 (functional) / 672 (BGA balls) |
| Internal Frequency (max) | — | [DATA_NEEDED: max internal frequency in MHz] |
| Core Supply Voltage | — | 1.8 V |
| Process Technology | — | 0.15 µm all-layer copper |
| 工作溫度 | — | 0 °C to +85 °C (Industrial) |
| Package Type | — | 672-ball BGA, 45 x 45 mm, 1.27 mm pitch |
| 安裝類型 | — | Surface Mount |
| Configuration Interface | — | JTAG / Passive Serial |
| Design Tool | — | Quartus II (legacy MAX+PLUS II) |