EP20K60EFI144-2X vs EP20K60EFC144-2 比較

詳細並排比較 EP20K60EFI144-2X 由 Altera 與 EP20K60EFC144-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K60EFI144-2X EP20K60EFC144-2
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Obsolete
Device Family APEX 20KE —
Typical Gates 60,000 60,000
Logic Elements 2,560 2,560
Maximum Operating Frequency 200 MHz —
Process Technology 0.22 µm CMOS 0.18 µm CMOS
Core Supply Voltage (VCCINT) 1.8 V (range 1.71 V to 1.89 V) —
Propagation Delay (tpd) 2.41 ns —
User I/O Pins 93 —
Dedicated Inputs 4 —
Total Terminals 144 —
Package Type FBGA-144 (FineLine BGA, LBGA) —
Package Code LBGA —
Terminal Form Ball —
Architecture MultiCore (LUT + product-term + embedded memory) —
I/O Standard Support LVDS, 1.8 V I/O —
Speed Grade -2 (industrial, -2X suffix) —
工作溫度 -40 °C to +85 °C 0 °C to +85 °C (commercial)
Configuration Interface JTAG (IEEE 1149.1) / serial PROM / parallel PROM —
濕度敏感等級 (MSL) 3 —
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Series — APEX-20K
Family — APEX-20KE (Enhanced, 1.8 V core)
Total RAM Bits — 32,768
User I/O — 92 to 93
Core Supply Voltage — 1.71 V to 1.89 V
Internal Frequency (max) — 160 MHz
Propagation Delay — 1.72 ns
封裝 — 144-LQFP (also referenced as 144-FBGA 13x13 in some sources)
JTAG Support — IEEE 1149.1 boundary scan
I/O Standards — LVTTL, LVCMOS, PCI, GTL+
Configuration Method — Serial/Parallel passive, JTAG, EPC companion

資料表與資源

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