EP2A25F672C8 vs EP2A25F672I6 比較

詳細並排比較 EP2A25F672C8 由 Altera 與 EP2A25F672I6 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2A25F672C8 EP2A25F672I6
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Family APEX II (EP2A25) APEX II
Logic Elements 25,000 (typical gates) —
Maximum System Gates 40,960 —
Macrocells / Embedded Logic 2,432 macros —
User I/O Count 492 —
封裝 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch) 672-ball FineLine BGA (FBGA-672)
Propagation Delay (tpd) 1.69 ns —
Speed Grade C8 6
工作溫度 0 C to 85 C (commercial) —
Process Technology 0.15 microm CMOS, 8-layer copper interconnect 0.18 µm CMOS
I/O Standards Supported LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL —
LVDS Data Rate 1 Gbps —
PLL Count 4 —
Embedded Memory ESB blocks (dual-port RAM, FIFO, CAM, ROM) Embedded System Blocks (ESB), dual-port RAM / CAM
I/O Banks 16 —
安裝類型 Surface Mount Surface Mount (BGA)
RoHS 狀態 Non-compliant (legacy product) [DATA_NEEDED: RoHS compliance status]
Logic Elements (typical gates) — 25,000
Fabric Architecture — SRAM-based LUT
Core Voltage — 1.5 V
Configuration Method — External SRAM configuration device (EPC series)
Temperature Grade — Industrial (-40 °C to +100 °C ambient)
DSP Blocks — MultiCore dedicated multipliers
Boundary Scan — JTAG (IEEE 1149.1) compliant
Clock Management — Dedicated PLL / clock tree circuitry
I/O Bank Count — [DATA_NEEDED: number of user I/O banks]
Lead-Free — [DATA_NEEDED: lead-free status]
MSL 等級 — [DATA_NEEDED: moisture sensitivity level]

資料表與資源

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