EP2A40B724I-8 vs EP2A40B724C7 比較

詳細並排比較 EP2A40B724I-8 由 Altera 與 EP2A40B724C7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2A40B724I-8 EP2A40B724C7
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Obsolete
Family APEX II APEX II
Logic Elements (LEs) 38,400 —
Logic Array Blocks (LABs) 3,840 —
Embedded System RAM 655,360 bits (655 Kbits) —
Maximum User I/O 540 540
封裝 724-ball FineLine BGA 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm
Package Code HBGA / S-PBGA-B724 —
Speed Grade -8 —
工作溫度 -40C to +100C (Industrial) 0 °C to +85 °C (commercial)
Core Supply Voltage 1.5 V (1.425 V to 1.575 V) 1.425 V to 1.575 V (typ. 1.5 V)
I/O Banks [DATA_NEEDED: I/O bank count] —
PLLs 4 4
安裝類型 Surface Mount Surface Mount (BGA)
RoHS 狀態 [DATA_NEEDED: RoHS status] Non-compliant (lead-bearing FCBGA)
Configuration Mode JTAG / passive serial / passive parallel —
Process Node [DATA_NEEDED: process technology] —
Logic Elements / Cells — 38,400
Total System Gates — 1,500,000
Embedded RAM Bits — 655,360
Process Technology — 0.15 µm CMOS, up to 8 metal layers, all-layer copper
Maximum Internal Frequency — 562 MHz
I/O Standards Supported — LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps)
Configuration Method — JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices
MultiVolt I/O Support — 1.5 V, 1.8 V, 2.5 V, 3.3 V
DDR Memory Support — Yes (via ESB / I/O circuitry)
MSL 等級 — [DATA_NEEDED: MSL level]

資料表與資源

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