EP2A40F1020C7N vs EP2A40F1020C7ES 比較

詳細並排比較 EP2A40F1020C7N 由 Intel 與 EP2A40F1020C7ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2A40F1020C7N EP2A40F1020C7ES
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX II APEX II
Technology 0.15 µm all-layer copper CMOS, up to 8 metal layers —
System Gates 1,500,000 (1.5 M) —
Logic Elements 38,400 38,400
Embedded Memory ESB-based, 504 Kbits total 655,360 bits
Maximum Internal Performance 562 MHz —
Propagation Delay 1.55 ns —
User I/O Pins 735 —
PLLs 4 Up to 8 (per datasheet family feature)
Clock Networks 12 —
True-LVDS Data Rate 1 Gbps —
Supported I/O Standards True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, SSTL —
Core Supply Voltage 1.5 V nominal (1.425 V – 1.575 V) —
Logic Family CMOS —
封裝 FC-FBGA-1020, 33 × 33 mm, 1.0 mm pitch, fine-line 1020-pin FC-FBGA
工作溫度 0 °C to +85 °C (commercial, C7 grade) [DATA_NEEDED: commercial/industrial grade]
Terminal Form BGA ball (flip-chip) —
安裝類型 Surface Mount Surface Mount (FC-FBGA)
Typical Gates — 1,500,000
Maximum User I/O — 735
Maximum Frequency — 562 MHz
Process Technology — 0.15 µm CMOS, all-layer copper, up to 8 metal layers
Core Voltage — 1.5 V
Speed Grade — C7 (with ES enhanced speed suffix)
High-Speed Interface — 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport
I/O Standards — LVTTL, LVCMOS, LVDS, LVPECL, PCML, HyperTransport, 1.5/1.8/2.5/3.3 V
RoHS 狀態 — [DATA_NEEDED]
Programming Interface — JTAG (IEEE 1149.1), passive serial

資料表與資源

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