EP2A40F1020C8N vs EP2A40F1020C9N 比較

詳細並排比較 EP2A40F1020C8N 由 Intel 與 EP2A40F1020C9N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2A40F1020C8N EP2A40F1020C9N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Product Type Field-Programmable Gate Array (FPGA) —
Device Family APEX II —
Logic Technology CMOS —
Logic Gates 1.5 million —
Logic Cells 38,400 —
Nominal Supply Voltage 1.5 V —
Supply Voltage Range 1.425 V to 1.575 V —
User I/Os 735 —
Package Terminal Count 1,020 pins —
Package Type FC-FBGA, BGA-1020 —
Package Body Size 33 mm x 33 mm —
Ball Pitch 1 mm —
Reported Operating Frequency 376 MHz —
Alternative Reported Frequency 562 MHz —
Reported Propagation Delay 1.78 ns —
Alternative Reported Propagation Delay 1.55 ns —
Fabrication Process 0.15 µm —
Maximum Reported Metal Layers 8 layers —
工作溫度 0 °C to 85 °C 0 °C to 85 °C
安裝類型 Surface Mount Surface Mount (BGA)
Terminal Form Ball —
RoHS 狀態 unknown unknown
REACH Status unknown —
AEC-Q100 Qualification unknown —
Family — APEX II
Series — EP2A40
Device Type — FPGA (Field-Programmable Gate Array)
Logic Family — CMOS
System Gates — 1.5 M
Logic Cells / Elements — 38,400
Maximum Operating Frequency — 366 MHz
Propagation Delay — 1.55 ns
Core Voltage — 1.5 V
Process Technology — 0.15 µm all-layer copper (up to 8 metal layers)
User I/O Pins — 735
Total Pins — 1020
封裝 — 1020-ball FC-FBGA, 33 × 33 mm, 1 mm pitch, FineLine
I/O Standards — True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, GTL+, SSTL
Configuration Modes — Passive Serial, Passive Parallel, JTAG
On-chip Memory — Embedded System Blocks (ESB) for RAM/ROM

資料表與資源

瀏覽所有產品 建立 BOM 索取報價