EP2A40F1020I9N vs EP2A40F1020C9N 比較
詳細並排比較 EP2A40F1020I9N 由 Intel 與 EP2A40F1020C9N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A40F1020I9N | EP2A40F1020C9N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Device Logic Elements / Cells | 38,400 cells | — |
| System Gates | 1,500,000 (1.5 M) | 1.5 M |
| Maximum Operating Frequency | 366 MHz | 366 MHz |
| Process Technology | 0.15 um CMOS, up to 8 metal layers | 0.15 µm all-layer copper (up to 8 metal layers) |
| Core Supply Voltage | 1.5 V | — |
| User I/O Count | 735 bidirectional I/O | — |
| 封裝 | 1020-pin FC-FBGA (Flip-Chip FineLine BGA) | 1020-ball FC-FBGA, 33 × 33 mm, 1 mm pitch, FineLine |
| Operating Temperature Grade | Industrial (I9 suffix: -40C to +100C per Altera APEX II convention) | — |
| High-Speed I/O Standards | True-LVDS (up to 1 Gbps), LVPECL, PCML, HyperTransport | — |
| Embedded Memory | ESB-based True-Dual-Port/Single-Port RAM, ROM, CAM (bits [DATA_NEEDED: total RAM bits]) | — |
| Clock Management | PLLs (count [DATA_NEEDED: PLL count]) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous/Synchronous, JTAG | Passive Serial, Passive Parallel, JTAG |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | unknown |
| 生命週期狀態 | Obsolete (per distributor listings / Altera APEX II family EOL) | — |
| Series | — | EP2A40 |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Logic Family | — | CMOS |
| Logic Cells / Elements | — | 38,400 |
| Propagation Delay | — | 1.55 ns |
| Core Voltage | — | 1.5 V |
| User I/O Pins | — | 735 |
| Total Pins | — | 1020 |
| 工作溫度 | — | 0 °C to 85 °C |
| I/O Standards | — | True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, GTL+, SSTL |
| On-chip Memory | — | Embedded System Blocks (ESB) for RAM/ROM |