EP2A70B724C7 vs EP2A70B724C7N 比較

詳細並排比較 EP2A70B724C7 由 Intel 與 EP2A70B724C7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2A70B724C7 EP2A70B724C7N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Unknown Obsolete
Device Type FPGA (Field Programmable Gate Array) FPGA (Field Programmable Gate Array)
Family APEX II APEX II (EP2A70)
Gate Count 3,000,000 gates —
Logic Cells 67,200 cells —
I/O Count 540 I/O —
Configuration or Memory Capacity [DATA_NEEDED: exact embedded-memory or configuration-memory capacity] —
供應電壓 1.5 V —
Maximum Frequency 420 MHz —
Fabrication Process 0.15 µm —
Loadable PLD Timing 2.17 ns —
Technology CMOS 0.15 µm CMOS
封裝 724-pin FCBGA, 724-BBGA, or PBGA724 724-pin FCBGA (Flip-Chip BGA)
Package Body Size 35 mm x 35 mm —
Package Pitch 1.27 mm —
Interface Capabilities True-LVDS, LVPECL, PCML, and HyperTransport —
RoHS 狀態 unknown [DATA_NEEDED: RoHS status]
REACH Status unknown —
AEC-Q100 Status unknown —
Lead-Free Status unknown —
工作溫度 [DATA_NEEDED: operating-temperature range] 0 °C to +85 °C (Commercial)
System Gates — 3,000,000
Logic Cells / Logic Elements — 67,200
Maximum Internal Frequency — 420 MHz
Propagation Delay (typ.) — 2.17 ns
User I/O Pins — 536
Macrocells (memory blocks reference) — 16
Core Supply Voltage — 1.5 V nominal
I/O Supply Voltage — MultiVolt (1.5V / 1.8V / 2.5V / 3.3V / 5V tolerant)
Ball Pitch — 1.27 mm
Seated Height — 3.5 mm
安裝類型 — Surface Mount
Configuration Method — JTAG, Passive Serial (PS), Fast Passive Parallel (FPP)
PLL Count — [DATA_NEEDED: PLL count]
Embedded Memory — Embedded System Blocks (ESBs) - dual-port RAM / ROM / CAM

資料表與資源

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