EP2AGZ350FF35C3G vs EP2AGZ350FF35I3 比較

詳細並排比較 EP2AGZ350FF35C3G 由 Altera 與 EP2AGZ350FF35I3 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2AGZ350FF35C3G EP2AGZ350FF35I3
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 NRND
Family Arria II GZ —
Logic Elements (LE) 350,000 348,500
Embedded Memory 16,860 Kbits —
DSP Blocks (18x18 Multipliers) 224 —
Transceivers 8 Up to 16 channels
Transceiver Data Rate up to 6.375 Gbps 6.375 Gbps
User I/O Pins 554 —
PLLs 8 —
Hard Memory Controllers 2 —
Memory Interface Support DDR3, DDR2, QDR II+, RLDRAM II —
Maximum Memory Clock 800 MHz —
Process Node 40 nm TSMC 40 nm
封裝 1152-FBGA (35 mm x 35 mm, 1.0 mm pitch) 1152-ball FCBGA (FF35)
工作溫度 0C to +85C (commercial) —
Core Voltage 0.9 V —
Configuration Modes Passive Serial, Fast Passive Parallel, JTAG, AS —
RoHS 狀態 Compliant Compliant per distributor listings
安裝類型 Surface Mount (BGA) —
Series — Arria II GZ
Embedded Memory Bits — 21,270,528 bits
Embedded Memory (M9K/M144K) — [DATA_NEEDED: block count and distribution]
Maximum User I/O — 554
DSP Blocks (18x19 multipliers) — [DATA_NEEDED: exact multiplier count, datasheet lists up to ~1,368]
Ball Pitch — 1.0 mm
Operating Temperature Grade — Industrial (-40C to +100C Tj)
Supply Voltage (Core) — 0.9 V typical [DATA_NEEDED: full range from datasheet]
Configuration Method — FPGA configuration via Altera Quartus II
Hard IP Blocks — PCIe Gen2 hard IP, memory controllers, PLLs
MSL 等級 — 3 (per typical Altera FCBGA handling)

資料表與資源

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