EP2C50F672C6 vs EP2C50F672C7 比較
詳細並排比較 EP2C50F672C6 由 Intel 與 EP2C50F672C7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2C50F672C6 | EP2C50F672C7 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 最後購買 |
| Series | Cyclone II | — |
| Logic Elements (LE) | 50,528 | 50,528 |
| Configurable Logic Blocks (CLB) | 3,158 | — |
| Embedded Memory Bits | 594,432 bits | 594,432 bits |
| Maximum User I/O | 450 | — |
| Maximum Internal Clock Frequency | 500 MHz | — |
| PLLs | 4 | — |
| Embedded 18x18 Multipliers | Yes (DSP blocks) | 86 (150 per device family datasheet figure) |
| Process Technology | 90 nm CMOS | 90 nm CMOS with low-k dielectric |
| Core Supply Voltage (VCCINT) | 1.2 V | — |
| 封裝 | 672-ball FBGA (FineLine BGA) | 672-ball FineLine BGA (FBGA-672) |
| 安裝類型 | Surface Mount | — |
| Configuration Modes | JTAG, Active Serial, Passive Serial | Passive Serial (PS), Active Serial (AS), JTAG |
| Operating Temperature Grade | Commercial (0 C to +85 C) - C6 speed grade | — |
| RoHS 狀態 | Compliant | — |
| Family | — | Cyclone II |
| Embedded Memory Blocks | — | 250 M4K blocks (4 Kbit each) |
| User I/O Pins | — | 450 |
| Phase-Locked Loops (PLL) | — | 4 |
| Global Clock Networks | — | 16 |
| Core Voltage (VCCINT) | — | 1.2 V |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V (per bank) |
| Speed Grade | — | -7 |
| Temperature Grade | — | Commercial (0C to +85C junction) |
| Lead-Free / RoHS | — | Lead-Free / RoHS compliant per Heisener listing |