EP2S60F672C3N vs EP2S60F672C4N 比較

詳細並排比較 EP2S60F672C3N 由 Intel 與 EP2S60F672C4N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2S60F672C3N EP2S60F672C4N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Obsolete
Family Stratix II Stratix II
Logic Elements (LE) 60,440 60,440
Logic Array Blocks (LABs) 3,022 —
Adaptive Logic Modules (ALMs) 24,176 —
Total Embedded Memory 2,544,192 bits (2.5 Mbits) —
User I/O Pins 492 —
User I/O Banks 8 —
Process Technology 90 nm CMOS 90 nm
Core Supply Voltage (VCCINT) 1.2 V —
I/O Supply Voltage (VCCIO) 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) —
Pre-Driver Supply (VCCPD) 3.3 V —
Maximum Internal Clock Frequency 816.99 MHz —
PLLs 4 —
Global Clock Networks 16 —
封裝 672-pin FC-FBGA 672-pin FC-FBGA
安裝類型 Surface Mount Surface Mount
工作溫度 0C to +85C (commercial grade) 0C to +85C (commercial)
Speed Grade C3 (slower speed grade) C4 (commercial)
RoHS 狀態 unknown —
Lead-Free unknown —
Adaptive Logic Modules (ALM) — 24,176
Embedded Memory (bits) — 2,544,192
Embedded Multiplier Blocks — [DATA_NEEDED: 9x9 multiplier count]
DSP Blocks — [DATA_NEEDED: DSP block count]
Maximum User I/O — 492
Core Voltage — 1.2 V
Maximum Fabric Clock — 711.24 MHz
Package Type — FineLine Ball-Grid Array
Configuration Method — JTAG, Fast Passive Parallel, Active Serial
MSL 等級 — 3
Lead-Free / RoHS — Yes (lead-free finish)

資料表與資源

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